ds001-1 (v2.3) november 1, 2001 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. introduction the spartan?-ii 2.5v field-programmable gate array fam- ily gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. the six-member family offers densities ranging from 15,000 to 200,000 system gates, as shown in table 1 . system perfor- mance is supported up to 200 mhz. spartan-ii devices deliver more gates, i/os, and features per dollar than other fpgas by combining advanced pro- cess technology with a streamlined virtex-based architec- ture. features include block ram (to 56k bits), distributed ram (to 75,264 bits), 16 selectable i/o standards, and four dlls. fast, predictable interconnect means that successive design iterations continue to meet timing requirements. the spartan-ii family is a superior alternative to mask-programmed asics. the fpga avoids the initial cost, lengthy development cycles, and inherent risk of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement necessary (impossible with asics). features second generation asic replacement technology - densities as high as 5,292 logic cells with up to 200,000 system gates - streamlined features based on virtex architecture - unlimited reprogrammability - very low cost system level features - selectram+? hierarchical memory: 16 bits/lut distributed ram configurable 4k bit block ram fast interfaces to external ram - fully pci compliant - low-power segmented routing architecture - full readback ability for verification/observability - dedicated carry logic for high-speed arithmetic - dedicated multiplier support - cascade chain for wide-input functions - abundant registers/latches with enable, set, reset - four dedicated dlls for advanced clock control - four primary low-skew global clock distribution nets - ieee 1149.1 compatible boundary scan logic versatile i/o and packaging - low cost packages available in all densities - family footprint compatibility in common packages - 16 high-performance interface standards - hot swap compact pci friendly - zero hold time simplifies system timing fully supported by powerful xilinx development system - foundation ise series: fully integrated software - alliance series: for use with third-party tools - fully automatic mapping, placement, and routing 0 spartan-ii 2.5v fpga family: introduction and ordering information ds001-1 (v2.3) november 1, 2001 00 preliminary product specification r table 1: spartan-ii fpga family members device logic cells system gates (logic and ram) clb array (r x c) total clbs maximum available user i/o (1) total distributed ram bits total block ram bits xc2s15 432 15,000 8 x 12 96 86 6,144 16k xc2s30 972 30,000 12 x 18 216 132 13,824 24k xc2s50 1,728 50,000 16 x 24 384 176 24,576 32k xc2s100 2,700 100,000 20 x 30 600 196 38,400 40k xc2s150 3,888 150,000 24 x 36 864 260 55,296 48k xc2s200 5,292 200,000 28 x 42 1,176 284 75,264 56k notes: 1. all user i/o counts do not include the four global clock/user input pins. see details in table 3, page 3 .
spartan-ii 2.5v fpga family: introduction and ordering information 2 www.xilinx.com ds001-1 (v2.3) november 1, 2001 1-800-255-7778 preliminary product specification r general overview the spartan-ii family of fpgas have a regular, flexible, pro- grammable architecture of configurable logic blocks (clbs), surrounded by a perimeter of programmable input/output blocks (iobs). there are four delay-locked loops (dlls), one at each corner of the die. two columns of block ram lie on opposite sides of the die, between the clbs and the iob columns. these functional elements are interconnected by a powerful hierarchy of versatile routing channels (see figure 1 ). spartan-ii fpgas are customized by loading configuration data into internal static memory cells. unlimited reprogram- ming cycles are possible with this approach. stored values in these cells determine logic functions and interconnec- tions implemented in the fpga. configuration data can be read from an external serial prom (master serial mode), or written into the fpga in slave serial, slave parallel, or boundary scan modes. spartan-ii fpgas are typically used in high-volume applica- tions where the versatility of a fast programmable solution adds benefits. spartan-ii fpgas are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. spartan-ii fpgas achieve high-performance, low-cost operation through advanced architecture and semiconduc- tor technology. spartan-ii devices provide system clock rates up to 200 mhz. spartan-ii fpgas offer the most cost-effective solution while maintaining leading edge per- formance. in addition to the conventional benefits of high-volume programmable logic solutions, spartan-ii fpgas also offer on-chip synchronous single-port and dual-port ram (block and distributed form), dll clock driv- ers, programmable set and reset on all flip-flops, fast carry logic, and many other features. the xilinx xc17s00a prom family is recommended for serial configuration of spartan-ii fpgas. the in-system programmable (isp) xc18v00 prom family is recom- mended for parallel or serial configuration. figure 1: basic spartan-ii family fpga block diagram xc2s15 dll dll dll dll block ram block ram block ram block ram i/o logic clbs clbs clbs clbs ds001_01_091800
spartan-ii 2.5v fpga family: introduction and ordering information ds001-1 (v2.3) november 1, 2001 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r spartan-ii product availability table 2 shows the package and speed grades available for spartan-ii family devices. ta b l e 3 shows the maximum user i/os available on the device and the number of user i/os available for each device/package combination. the four global clock pins are usable as additional user i/os when not used as a global clock pin. these pins are not included in user i/o counts. table 2: spartan-ii package and speed grade availability device pins 100 144 144 208 256 456 type plastic vqfp plastic tqfp chip scale bga plastic pqfp fine pitch bga fine pitch bga code vq100 tq144 cs144 pq208 fg256 fg456 xc2s15 -5 c, i c, i c, i - - - -6ccc - - - xc2s30-5 c, ic, ic, ic, i - - -6cccc - - xc2s50 -5 - c, i - c, i c, i - -6-c-cc- xc2s100 -5 - c, i - c, i c, i c, i -6-c-ccc xc2s150 -5 - - - c, i c, i c, i -6---ccc xc2s200 -5 - - - c, i c, i c, i -6---ccc notes: 1. c = commercial, t j = 0 to +85 c; i = industrial, t j = ? 40 c to +100 c. table 3: spartan-ii user i/o chart (1) device maximum user i/o available user i/o according to package type vq100 tq144 cs144 pq208 fg256 fg456 xc2s15 86 60 86 86 - - - xc2s30 132 60 92 92 132 - - xc2s50 176 - 92 - 140 176 - xc2s100 196 - 92 - 140 176 196 xc2s150 260 - - - 140 176 260 xc2s200 284 - - - 140 176 284 notes: 1. all user i/o counts do not include the four global clock/user input pins.
spartan-ii 2.5v fpga family: introduction and ordering information 4 www.xilinx.com ds001-1 (v2.3) november 1, 2001 1-800-255-7778 preliminary product specification r ordering information revision history the spartan-ii family data sheet ds001-1 , spartan-ii 2.5v fpga family: introduction and ordering information (module 1) ds001-2 , spartan-ii 2.5v fpga family: functional description (module 2) ds001-3 , spartan-ii 2.5v fpga family: dc and switching characteristics (module 3) ds001-4 , spartan-ii 2.5v fpga family: pinout tables (module 4) xc2s50 -6 pq 208 c example: temperature range number of pins package type device type speed grade device ordering options device speed grade number of pins / package type temperature range (t j ) xc2s15 -5 standard performance vq100 100-pin plastic very thin qfp c = commercial 0 c to +85 c xc2s30 -6 higher performance cs144 144-ball chip-scale bga i = industrial ? 40 c to +100 c xc2s50 tq144 144-pin plastic thin qfp xc2s100 pq208 208-pin plastic qfp xc2s150 fg256 256-ball fine pitch bga xc2s200 fg456 456-ball fine pitch bga version no. date description 2.0 09/18/00 sectioned the spartan-ii family data sheet into four modules. added industrial temperature range information. 2.1 10/31/00 removed power down feature. 2.2 03/05/01 added statement on proms. 2.3 11/01/01 update product availability chart. minor text edits. pn 011311
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